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ICS854S054I 4:1 Differential-to-LVDS Clock Multiplexer

ICS854S054I Description

4:1 Differential-to-LVDS Clock Multiplexer ICS854S054I DATA SHEET General .
The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.

ICS854S054I Features

* High speed 4:1 differential multiplexer
* One differential LVDS output pair
* Four selectable differential PCLK, nPCLK input pairs
* PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML
* Maximum output frequency: 2.5GHz

ICS854S054I Applications

* Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the requi

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Differential-to-LVDS Clock Multiplexer Integrated Device Technology
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