MK2049-02 - Communications Clock PLLs

Integrated Circuit Systems

Datasheet Details

Part number	MK2049-02
Manufacturer	Integrated Circuit Systems
File Size	148.25 KB
Description	Communications Clock PLLs
Datasheet	MK2049-02_IntegratedCircuitSystems.pdf

The MK2049-02 and MK2049-03 are PhaseLocked Loop (PLL) based clock synthesizers that accept multiple input frequencies.

Packaged in 20 pin SOIC.
Fixed input-output phase relationship on most clock selections.
Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E.
Accept multiple inputs: 8 kHz backplane clock, Loop Timing frequencies, or 10-28 MHz.
Lock to 8 kHz ±100 ppm (External mode).
Buffer Mode allows jitter attenuation of 10.
28 MHz input and x1/x0.

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Published: May 7, 2005 |