Datasheet Specifications
- Part number
- M2020
- Manufacturer
- Integrated Circuit Systems
- File Size
- 431.78 KB
- Datasheet
- M2020_IntegratedCircuitSystems.pdf
- Description
- VCSO BASED CLOCK PLL
Description
Integrated Circuit Systems, Inc.Product Data Sheet M2020/21 VCSO BASED CLOCK PLL GENERAL .
Features
* Integrated SAW (surface acoustic wave) delay line; low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz)Applications
* to assure PLL tracking, especially during GR-253 jitter tolerance testing. The recommended maximum phase detector frequency for loop timing mode is 19.44MHz. When LOL is to be used for system health monitoring, the phase detector frequency should be 5MHz or greater. Low phase detector frequencies maM2020 Distributors
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