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IS61NVP51236 - (IS61NVPxxxxx) STATE BUS SRAM

Download the IS61NVP51236 datasheet PDF. This datasheet also covers the IS61NVP25672 variant, as both devices belong to the same (is61nvpxxxxx) state bus sram family and are provided as variant models within a single manufacturer datasheet.

Description

The 18 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications.

Features

  • www. DataSheet4U. com ISSI JULY 2006 ®.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61NVP25672_ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61NVP102436A 36Mb STATE BUS SRAM Integrated Silicon Solution
IS61NVP204818A 36Mb STATE BUS SRAM Integrated Silicon Solution
IS61NVP204836B PIPELINE (NO WAIT) STATE BUS SRAM Integrated Silicon Solution
IS61NVP409618B PIPELINE (NO WAIT) STATE BUS SRAM Integrated Silicon Solution
IS61NVF102418 STATE BUS SRAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61NVP51236B 18Mb STATE BUS SYNCHRONOUS SRAM
IS61NVP51232B 18Mb STATE BUS SYNCHRONOUS SRAM
IS61NVP51218A 9Mb STATE BUS SRAM
IS61NVP51218B 9Mb STATE BUS SRAM
IS61NVP10018 (IS61NVP10018 / IS61NVP51236) State Bus SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES www.DataSheet4U.com ISSI JULY 2006 ® DESCRIPTION The 18 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read.
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