IDT74SSTUBH32868A Datasheet (IDT) - 28-BIT CONFIGURABLE REGISTERED BUFFER

IDT74SSTUBH32868A, 28-BIT CONFIGURABLE REGISTERED BUFFER

This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation.

All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS.

All outputs are edge-controlled circuits opti

www.DataSheet4U.com DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 IDT74SSTUBH32868A occurred on the open-drain QERR pin (active low).

The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit.

To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state.

If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock

IDT74SSTUBH32868A Features

* 28-bit 1:2 registered buffer with parity check functionality

* Supports SSTL_18 JEDEC specification on data inputs and outputs Applications

* Twice the output drive to support heavily loaded RDIMMs

* DDR2 Memory Modules

* Provides complete DDR DIMM solution