IDT74SSTUBF32869A Datasheet - IDT

IDT74SSTUBF32869A 14-BIT CONFIGURABLE REGISTERED BUFFER

The IDT74SSTUBF32869A is 14-bit 1:2 registered buffer with parity, designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers optimized to drive the DDR2 DIMM load. They pro.

IDT74SSTUBF32869A Features

* 14-bit 1:2 registered buffer with parity check functionality

* Supports SSTL_18 JEDEC specification on data inputs and outputs

* 50% more dynamic driver strength than standard SSTU32864

* Supports LVCMOS switching levels on C1 and RESET inputs

* Low volta

IDT74SSTUBF32869A Datasheet (393.47 KB)