IDT74SSTUBH32865A Datasheet (IDT) - 28-BIT 1:2 REGISTERED BUFFER

IDT74SSTUBH32865A, 28-BIT 1:2 REGISTERED BUFFER

This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18.

The control inputs are LVCMOS.

All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load.

The IDT74SST

IDT74SSTUBH32865A Features

* Double Drive strength for heavily-loaded DIMM applications

* 28-bit 1:2 registered buffer with parity check functionality

* Supports SSTL_18 JEDEC specification on data inputs

* and outputs Supports LVCMOS switching levels on CSGateEN and RESET