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IDT71P73804 - 18Mb Pipelined DDRII SRAM

Download the IDT71P73804 datasheet PDF (IDT71P73104 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 18mb pipelined ddrii sram.

Description

The IDT DDRIITM Burst of four SRAMs are high-speed synchronous memories with a double-data-rate (DDR), bidirectional data port.

This scheme allows maximization on the bandwidth on the data bus by passing two data items per clock cycle.

Features

  • IDT71P73204 IDT71P73104 IDT71P73804 IDT71P73604.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT71P73104_IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT71P73804
Manufacturer IDT
File Size 668.16 KB
Description 18Mb Pipelined DDRII SRAM
Datasheet download datasheet IDT71P73804 Datasheet

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Other Datasheets by IDT
  • IDT71P73104 - 18Mb Pipelined DDRII SRAM
  • IDT71P73204 - 18Mb Pipelined DDRII SRAM
  • IDT71P73604 - 18Mb Pipelined DDRII SRAM
  • IDT71P71104 - (IDT71P71x04) 18Mb Pipelined DDRII SRAM Burst of 2
  • IDT71P71204 - (IDT71P71x04) 18Mb Pipelined DDRII SRAM Burst of 2
  • IDT71P71604 - (IDT71P71604 / IDT71P71804) 18Mb Pipelined DDRII SRAM Burst of 2
  • IDT71P71804 - (IDT71P71604 / IDT71P71804) 18Mb Pipelined DDRII SRAM Burst of 2
  • IDT71P72104 - (IDT71P72x04) 18Mb Pipelined QDRII SRAM Burst of 2

Full PDF Text Transcription

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18Mb Pipelined DDR™II SRAM Burst of 4 Features ◆ ◆ ◆ ◆ ◆ IDT71P73204 IDT71P73104 IDT71P73804 IDT71P73604 Description The IDT DDRIITM Burst of four SRAMs are high-speed synchronous memories with a double-data-rate (DDR), bidirectional data port. This scheme allows maximization on the bandwidth on the data bus by passing two data items per clock cycle. The address bus operates at less than single data rate speeds,allowing the user to fan out addresses and ease system design while maintaining maximum performance on data transfers. The DDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. All interfaces of the DDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface.
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