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IDT71P71604 - (IDT71P71604 / IDT71P71804) 18Mb Pipelined DDRII SRAM Burst of 2

Download the IDT71P71604 datasheet PDF. This datasheet also covers the IDT71P71804 variant, as both devices belong to the same (idt71p71604 / idt71p71804) 18mb pipelined ddrii sram burst of 2 family and are provided as variant models within a single manufacturer datasheet.

Description

The IDT DDRIITM Burst of two SRAMs are high-speed synchronous memories with a double-data-rate (DDR), bidirectional data port.

This scheme allows maximization of the bandwidth on the data bus by passing two data items per clock cycle.

Features

  • www. DataSheet4U. com.
  • IDT71P71804 IDT71P71604.

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Note: The manufacturer provides a single datasheet file (IDT71P71804_IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT71P71604
Manufacturer IDT
File Size 278.01 KB
Description (IDT71P71604 / IDT71P71804) 18Mb Pipelined DDRII SRAM Burst of 2
Datasheet download datasheet IDT71P71604 Datasheet

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Other Datasheets by IDT

Part Number Description
IDT71P71104 (IDT71P71x04) 18Mb Pipelined DDRII SRAM Burst of 2
IDT71P71204 (IDT71P71x04) 18Mb Pipelined DDRII SRAM Burst of 2
IDT71P71804 (IDT71P71604 / IDT71P71804) 18Mb Pipelined DDRII SRAM Burst of 2
IDT71P72104 (IDT71P72x04) 18Mb Pipelined QDRII SRAM Burst of 2
IDT71P72204 (IDT71P72x04) 18Mb Pipelined QDRII SRAM Burst of 2

Full PDF Text Transcription

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18Mb Pipelined DDR™II SRAM Burst of 2 Features ◆ ◆ ◆ ◆ ◆ www.DataSheet4U.com ◆ ◆ ◆ ◆ IDT71P71804 IDT71P71604 Description The IDT DDRIITM Burst of two SRAMs are high-speed synchronous memories with a double-data-rate (DDR), bidirectional data port. This scheme allows maximization of the bandwidth on the data bus by passing two data items per clock cycle. The address bus operates at single data rate speeds, allowing the user to fan out addresses and ease system design while maintaining maximum performance on data transfers. The DDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. All interfaces of the DDRII SRAM are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface.
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