M13S2561616A Datasheet (Elite Semiconductor Memory Technology) - 4M x 16 Bit x 4 Banks Double Data Rate SDRAM

M13S2561616A, 4M x 16 Bit x 4 Banks Double Data Rate SDRAM

Pin Name Function Address inputs - Row address A0~A12 - Column address A0~A8 A10/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Row address strobe Column address strobe Write enable Ground Power Bi-directional Data Strobe.

LDQS corresponds to the data on DQ0~DQ7; UDQS corresp

M13S2561616A Features

* z z z z z z z z z z z z z z z z z z z z M13S2561616A 4M x 16 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and