M13S128168A - Double Data Rate SDRAM

Elite Semiconductor Memory Technology

The M13S128168A by Elite Semiconductor Memory Technology is a Double Data Rate SDRAM. Below is the official datasheet preview.

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M13S128168A Double Data Rate SDRAM by Elite Semiconductor Memory Technology - Datasheet Preview — Official preview page of the **M13S128168A** Double Data Rate SDRAM datasheet (Elite Semiconductor Memory Technology).

Datasheet Details

Part number	M13S128168A
Manufacturer	Elite Semiconductor Memory Technology
File Size	1.76 MB
Description	Double Data Rate SDRAM
Datasheet	M13S128168A_EliteSemiconductorMemoryTechnology.pdf
Additional preview pages of the M13S128168A datasheet.

M13S128168A Product details

Description

Pin Name Function Pin Name Function A0~A11, BA0, BA1 Address inputs - Row address A0~A11 - Column address A0~A8 A10/AP: AUTO Precharge BA0, BA1: Bank selects (4 Banks) DM is an input mask signal for write data.LDM, UDM LDM corresponds to the data on DQ0~DQ7; UDM correspond to the data on DQ8~DQ15. DQ0~DQ15 Data-in/Data-out CLK, CLK Clock input RAS Row address strobe CAS Column address strobe WE Write enable VSS Ground VDD LDQS, UDQS Power Bi-directional Data Strobe.LDQS corres

Features

Double-data-rate architecture, two data transfers per clock cycle.
Bi-directional data strobe (DQS).
Differential clock inputs (CLK and CLK ).
DLL aligns DQ and DQS transition with CLK transition.
Four bank operation.
CAS Latency : 2, 2.5, 3.
Burst Type : Sequential and Interleave.
Burst Length : 2, 4, 8.
All inputs except data & DM are sampled at the rising edge of the system clock (CLK).
Data I/O transitions on both edges of data strobe (DQS).

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Published: Sep 17, 2009 |