The DFPMUL by Digital Core Design is a Floating Point Pipelined Multiplier Unit. Below is the official datasheet preview.
| Part number | DFPMUL |
|---|---|
| Manufacturer | Digital Core Design |
| File Size | 172.83 KB |
| Description | Floating Point Pipelined Multiplier Unit |
| Datasheet |
 DFPMUL_DigitalCoreDesign.pdf
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PIN clk rst en adatai[31:0] bdatai[31:0] datao[31:0] ofo ufo ifo TYPE Input Input Input Input Input DESCRIPTION Global system clock Global system reset Enable computing A data bus input B data bus input Output Data bus output Output Overflow flag Output Underflow flag Output Invalid result flag Speed grade -1 -1 -1 -1 -7 -7 -5 -5 -6 -3 -6 Logic Cells 1340 1340 1210 1210 1210 1210 1290 440+8M1 1170 410+8M1 480+8M1 Fmax 40 MHz 40 MHz 50 MHz 50 MHz 51 MHz 67 MHz 77 MHz 93 MHz 72 MHz 134 MHz 117
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