The DFPAU-DP by Digital Core Design is a Floating Point Arithmetic Coprocessor Double Precision. Below is the official datasheet preview.
| Part number | DFPAU-DP |
|---|---|
| Manufacturer | Digital Core Design |
| File Size | 188.90 KB |
| Description | Floating Point Arithmetic Coprocessor Double Precision |
| Datasheet |
 DFPAU-DP_DigitalCoreDesign.pdf
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PIN TYPE Input Input Input Input Input Input 2 DESCRIPTION Global system clock Global system reset Chip select for read/write Data bus input Register address to read/write Data write enable datai[31:0]1 addr[4:2] we datao[31:0]1 irq Output Data bus output Output Interrupt request indicator 1 data bus can be configured as 8-, 16- or 32- bit depends on processor’s bus size 2 address bus is aligned to work with 8- (3:0), 16(3:1) or 32- (4:2) bit processors BLOCK DIAGRAM Man
📁 DFPAU-DP Similar Datasheet
