Datasheet4U Logo Datasheet4U.com

CY7C1323BV25 - 18-Mbit 4-Word Burst SRAM

📥 Download Datasheet

Preview of CY7C1323BV25 PDF
datasheet Preview Page 2 datasheet Preview Page 3

CY7C1323BV25 Product details

Description

18-Mbit Density (512 Kbit x 36) 167-MHz Clock for high bandwidth 4-Word Burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 333 MHz @ 167 MHz) Two input clocks (K and K) for precise DDR timing SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches. Separate Port Selects for depth expansion Synchron

Features

📁 CY7C1323BV25 Similar Datasheet

  • CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C131E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C136AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C136E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
  • CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)
Other Datasheets by Cypress Semiconductor
Published: |