CY7C1241KV18 - 36-Mbit QDR II SRAM 4-Word Burst Architecture

Cypress Semiconductor

CY7C1241KV18 Datasheet Preview — Preview of CY7C1241KV18 PDF

Datasheet Details

Part number	CY7C1241KV18
Manufacturer	Cypress Semiconductor
File Size	Direct Link
Description	36-Mbit QDR II SRAM 4-Word Burst Architecture
Datasheet	CY7C1241KV18_CypressSemiconductor.pdf

CY7C1241KV18 Product details

Description

Functional Description The CY7C1241KV18, CY7C1256KV18, CY7C1243KV18, and CY7C1245KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture.Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array.The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.QDR II+ architectur

Features

Configurations With Read Cycle Latency of 2.0 cycles: CY7C1241KV18.
4 M × 8 CY7C1256KV18.
4 M × 9 CY7C1243KV18.
2 M × 18 CY7C1245KV18.
1 M × 36 Separate independent read and write data ports.
Supports concurrent transactions 450 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double data rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz Available in 2.0 clock cycle latency Two.

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Published: Apr 15, 2011 |