Description
The AS7C33512NTD18A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM) organized as 524,288 words × 18 bits and incorporates a LATE LATE Write.
Features
- Organization: 524,288 words × 18 bits.
- NTD™ architecture for efficient bus operation.
- Fast clock speeds to 166 MHz.
- Fast clock to data access: 3.5/4.0 ns.
- Fast OE access time: 3.5/4.0 ns.
- Fully synchronous operation www. DataSheet4U. com.
- Common data inputs and data outputs.
- Asynchronous output enable control.
- Available in100-pin TQFP.
- Byte write enables.
- Clock enable for operation hold.
- Mu.
AS7C33512NTD18A_AllianceSemiconductorCorporation.pdf