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74AVCH4T245 Datasheet Preview

74AVCH4T245 Datasheet

4-bit dual supply translating transceiver

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74AVCH4T245
4-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 5 — 17 December 2015
Product data sheet
1. General description
The 74AVCH4T245 is a 4-bit, dual supply transceiver that enables bidirectional level
translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It
features two 2-bit input-output ports (nAn and nBn), a direction control input (nDIR), a
output enable input (nOE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and
VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable
for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and
3.3 V). Pins nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to
VCC(B). A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows
transmission from nBn to nAn. The output enable input (nOE) can be used to disable the
outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both nAn and nBn outputs are in the high-impedance OFF-state. The bus hold
circuitry on the powered-up side always stays active.
The 74AVCH4T245 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features and benefits
Wide supply voltage range:
VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
380 Mbit/s (1.8 V to 3.3 V translation)




nexperia

74AVCH4T245 Datasheet Preview

74AVCH4T245 Datasheet

4-bit dual supply translating transceiver

No Preview Available !

Nexperia
74AVCH4T245
4-bit dual supply translating transceiver; 3-state
200 Mbit/s (1.1 V to 3.3 V translation)
200 Mbit/s (1.1 V to 2.5 V translation)
200 Mbit/s (1.1 V to 1.8 V translation)
150 Mbit/s (1.1 V to 1.5 V translation)
100 Mbit/s (1.1 V to 1.2 V translation)
Suspend mode
Bus hold on data inputs
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
74AVCH4T245D 40 C to +125 C SO16
plastic small outline package; 16 leads;
body width 3.9 mm
74AVCH4T245PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
74AVCH4T245BQ 40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
74AVCH4T245GU 40 C to +125 C XQFN16
plastic, extremely thin quad flat package; no leads;
16 terminals; body 1.80 2.60 0.50 mm
Version
SOT109-1
SOT403-1
SOT763-1
SOT1161-1
4. Marking
Table 2. Marking codes
Type number
74AVCH4T245D
74AVCH4T245PW
74AVCH4T245BQ
74AVCH4T245GU
Marking code
74AVCH4T245D
CH4T245
H4T245
K4
74AVCH4T245
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 17 December 2015
© Nexperia B.V. 2017. All rights reserved
2 of 29


Part Number 74AVCH4T245
Description 4-bit dual supply translating transceiver
Maker nexperia
Total Page 29 Pages
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