74AVCH2T45 Datasheet | Nexperia

description The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (n A and n B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins n A and DIR are referenced to VCC(A) and pins n B are referenced to VCC(B). A HIGH on DIR allows transmission from n A to n B and a LOW on DIR allows transmission from n B to n A. The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state. The 74AVCH2T45 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2. Features and benefits - Wide supply voltage range: 0.8 V to 3.6 V for VCC(A) and VCC(B) - High noise immunity - Suspend mode - Bus hold on data inputs - Inputs accept voltages up to 3.6 V - Low noise overshoot and undershoot < 10 % of VCC - IOFF circuitry provides partial Power-down mode operation - Maximum data rates: - 500 Mbps (1.8 V to 3.3 V translation) - 320 Mbps (< 1.8 V to 3.3 V translation) - 320 Mbps (translate to 2.5 V or 1.8 V) - 280 Mbps (translate to 1.5 V) - 240 Mbps (translate to 1.2 V) - Latch-up performance exceeds 100 m A per JESD 78 Class II - plies with JEDEC standards: - JESD8-12 (0.8 V to 1.3 V) - JESD8-11 (0.9 V to 1.65 V) - JESD8-7 (1.2 V to 1.95 V) - JESD8-5 (1.8 V to 2.7 V) - JESD8-B (2.7 V to 3.6 V) - ESD protection: - HBM: ANSI/ESDA/Jedec JS-001 Class 3B exceeds 8000 V - CDM: ANSI/ESDA/Jedec JS-002 Class C3...