SN74SSTVF32852 datasheet, buffer equivalent, Texas Instruments

Application

D 1-to-2 Outputs Support Stacked DDR DIMMs D One Device Per DIMM Required D Output Edge-Control Circuitry Minimizes Swit.

Description

ordering information This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits, optimized for unterminated DIMM loads, .

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