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SN74SSTV16859 - 13-BIT TO 26-BIT REGISTERED BUFFER

General Description

This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET) input.

All outputs are SSTL_2, Class II compatible.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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D Member of the Texas Instruments Widebus Family D 1-to-2 Outputs to Support Stacked DDR DIMMs D Supports SSTL_2 Data Inputs D Outputs Meet SSTL_2 Class II Specifications D Differential Clock (CLK and CLK) Inputs D Supports LVCMOS Switching Levels on the RESET Input D RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low D Pinout Optimizes DIMM PCB Layout D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) description/ordering information This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.