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CDCLVD2102 - Dual 1:2 Low Additive Jitter LVDS Buffer

General Description

The CDCLVD2102 clock buffer distributes two clock inputs (IN0, IN1) to a total of 4 pairs of differential LVDS clock outputs (OUT0, OUT3).

Each buffer block consists of one input and 2 LVDS outputs.

The inputs can either be LVDS, LVPECL, or LVCMOS.

Key Features

  • 1.
  • Dual 1:2 Differential Buffer.
  • Low Additive Jitter.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 Dual 1:2 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2102 FEATURES 1 • Dual 1:2 Differential Buffer • Low Additive Jitter <300 fs RMS in 10-kHz to 20-MHz • Low Within Bank Output Skew of 15 ps (Max) • Universal Inputs Accept LVDS, LVPECL, LVCMOS • One Input Dedicated for Two Outputs • Total of 4 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible • Clock Frequency up to 800 MHz • 2.375–2.