CDCLVD2104 buffer equivalent, dual 1:4 low additive jitter lvds buffer.
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* Dual 1:4 Differential Buffer
* Low Additive Jitter <300 fs, RMS in
10 kHz to 20 MHz
* Low Within Bank Output Skew of 35ps (Max)
* Universal Inputs Acc.
* Telecommunications/Networking
* Medical Imaging
* Test and Measurement Equipment
* Wireless Communicat.
The CDCLVD2104 clock buffer distributes two clock inputs (IN0, IN1) to a total of 8 pairs of differential LVDS clock outputs (OUT0, OUT7). Each buffer block consists of one input and 4 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.
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