CDC208 drivers equivalent, dual 1-line to 4-line clock drivers.
D TTL-Compatible Inputs and
CMOS-Compatible Outputs
D Flow-Through Architecture Optimizes
PCB Layout
D Center-Pin VCC an.
The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1 and OE2) inputs for each circuit that can force the out.
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