A3S64D40GTP Datasheet, Zentel

- Vdd=VddQ=2.5V+0.2V (-50) - Double data rate architecture ; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Dif.

A3S64D40GTP is a 4-bank x 1,048,576-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and output da.

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