A3S56D30ETP Datasheet (A3S56D30ETP / A3S56D40ETP) 256Mb DDR SDRAM

Manufacturer: Zentel

Download the A3S56D30ETP datasheet PDF. This datasheet also includes the A3S56D40ETP variant, as both parts are published together in a single manufacturer document.

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A3S56D30ETP (a3s56d30etp / a3s56d40etp) 256mb ddr sdram by Zentel - Datasheet Preview — Note: The manufacturer provides a single datasheet file (A3S56D40ETP_Zentel.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number	A3S56D30ETP
Manufacturer	Zentel
File Size	952.32 KB
Description	(A3S56D30ETP / A3S56D40ETP) 256Mb DDR SDRAM
Datasheet	A3S56D30ETP Datasheet

General Description

A3S56D30ETP is a 4-bank x 8,388,608-word x 8bit, A3S56D40ETP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

All control and address signals are referenced to the rising edge of CLK.

Input data is registered on both edges of data strobe ,and output data and data strobe are referenced on both edges of CLK.

Overview

A3S56D30ETP A3S56D40ETP www.DataSheet4U.com 256M Double Data Rate Synchronous DRAM 256Mb DDR SDRAM Specification A3S56D30ETP A3S56D40ETP Zentel Electronics Corp.

6F-1, No.

1-1, R&D Rd.

Key Features

- Vdd=Vddq=2.5V+0.2V (-5E, -5, -6) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - /CAS latency - 2.0 / 2.5 / 3.0 (programmable) ; Burst.

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