A3S64D40GTP Datasheet 64M Double Data Rate Synchronous DRAM

Manufacturer: Zentel

Datasheet Details

Part number	A3S64D40GTP
Manufacturer	Zentel
File Size	1.54 MB
Description	64M Double Data Rate Synchronous DRAM
Datasheet	A3S64D40GTP Datasheet

A3S64D40GTP is a 4-bank x 1,048,576-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

All control and address signals are referenced to the rising edge of CLK.

Input data is registered on both edges of data strobe ,and output data and data strobe are referenced on both edges of CLK.

A3S64D40GTP 64M Double Data Rate Synchronous DRAM 64Mb DDR SDRAM Specification A3S64D40GTP Zentel Electronics Corp.

Revision 1.0 Nov.

- Vdd=VddQ=2.5V+0.2V (-50) - Double data rate architecture ; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0, BA1 (Bank Address) - CAS latency - 2 / 2.5 / 3 (programmable) - Burst length - 2 / 4 /.

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