A3S28D40FTP Datasheet, Zentel

- Vdd=VddQ=2.5V+0.2V (-4, -5E, -5) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with .

A3S28D30FTP is a 4-bank x 4,194,304-word x 8bit, A3S28D40FTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is regis.