ZL30101 Datasheet | Zarlink Semiconductor Inc

Features April 2010 - Supports Telcordia GR-1244-CORE Stratum 3 - Supports G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces - Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces - Simple hardware control interface - Accepts two input references and synchronizes to any bination of 8 k Hz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz inputs - Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz and either 4.096 MHz & 8.192 MHz or 32.768 MHz & 65.536 MHz - Hitless reference switching between any bination of valid input reference frequencies - Provides 5 styles of 8 k Hz framing pulses - Holdover frequency accuracy of 1 x 10-8 - Lock, Holdover and Out of Range indication - Selectable loop filter bandwidth of 1.8 Hz or 922 Hz - Less than 0.6 nspp jitter on all output clocks Ordering Information ZL30101QDG1 64 Pin TQFP- Trays, Bake & Drypack - Pb Free Matte Tin -40°C to +85°C - External master clock source: clock oscillator or crystal Applications - Synchronization and timing control for multi-trunk DS1/E1 systems such as DSLAMs, gateways and PBXs - Clock and frame pulse source for ST-BUS, GCI and other time division multiplex (TDM) buses REF0 REF1 OSCi OSCo TIE_CLR BW_SEL LOCK OUT_SEL Master Clock TIE Corrector Circuit Virtual Reference DPLL E1 Synthesizer REF_FAIL0 REF_FAIL1 Reference Monitor TIE Corrector Enable REF_SEL RST State Machine Mode Control Feedback Frequency Select MUX DS1...