WCSS0418V1P ram equivalent, 256k x 18 synchronous-pipelined cache ram.
* Supports 100-MHz bus for Pentium and PowerPC™ operations with zero wait states
* Fully registered inputs and outputs for pipelined operation
* 256K by 18 c.
The WCSS0418V1P is a 3.3V, 256K by 18 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.
Logic Block Diagram
CLK ADV ADSC ADSP A[17:0] GW BWE BW 1 BW0
MODE (A[1;0]) 2 BURST Q0 CE COUNTER Q1.
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