THC63LVD104C receiver equivalent, 112mhz 30bits color lvds receiver.
* Wide dot clock range: 8-112MHz suited for NTSC,
VGA, SVGA, XGA, and SXGA
* PLL requires no external components
* 50% output clock duty cycle
* TTL clock.
The THC63LVD104C receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104C converts the LVDS data streams back into 35bits of CMOS/TTL data with the choice of the ri.
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