THC63LVD104A receiver equivalent, 90mhz 30bits color lvds receiver.
* Wide dot clock range: 8-90MHz suited for NTSC,
VGA, SVGA, XGA, and WXGA
* PLL requires no external components
* 50% output clock duty cycle
* TTL clock .
The THC63LVD104A receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to WXGA resolutions. The THC63LVD104A converts the LVDS data streams back into 35bits of CMOS/TTL data with rising edge or falli.
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