THC63LVD103
Description
The THC63LVD103 transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA+ resolutions. The THC63LVD103 converts 35bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 135MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC, VSYNC, DE, CNTL1, CNTL2) are transmitted at an effective rate of 945Mbps per LVDS channel.
Features
- Wide dot clock range: 8-135MHz suited for NTSC,
VGA, SVGA, XGA,SXGA and SXGA+
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- PLL requires no external ponents Supports spread spectrum clock generator On chip jitter filtering Clock edge selectable Supports reduced swing LVDS for low EMI Power down mode Low power single 3.3V CMOS design 64pin TQFP Backward patible with THC63LVDM63R(18bits) / M83R(24bits)
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Block Diagram
CMOS/TTL INPUT
TA0-6 7
Data...
