ST1005SRG Datasheet | Stanson Technology

DESCRIPTION ST1005SRG is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook puter power management, other battery powered circuits, and low in-line power loss are required. The product is in a very small outline surface mount package. PIN CONFIGURATION SOT-23 FEATURE l- -100V/-0.8.0A, RDS(ON) = 650m-ohm (Typ.) @VGS = -10V l- -60V/-0.4A, RDS(ON) = 700m-ohm @VGS = -4.5V l- Super high density cell design for extremely low RDS(ON) l- Exceptional on-resistance and maximum DC current capability l- SOT-23 package design 1.Gate 2.Source 3.Drain PART MARKING SOT-23 105YA Y: Year Code A: Process Code STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA .stansontech. ST1005SRG 2013. Rev.1 P Channel Enhancement Mode MOSFET -0.8A ABSOULTE MAXIMUM RATINGS (Ta = 25℃ Unless otherwise noted ) Parameter Symbol Typical Drain-Source Voltage VDSS -100 Gate-Source Voltage Continuous Drain Current TJ=150℃) TA=25℃ TA=70℃ Pulsed Drain Current VGSS ID IDM ±20 -0.8 -0.4 -4 Continuous Source Current (Diode Conduction) Power Dissipation TA=25℃ TA=70℃ Operation Junction...