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K7A203600A - 64Kx36-Bit Synchronous Pipelined Burst SRAM

Description

The K7A203600A is a 2,359,296-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

Features

  • Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. Self-Timed Write Cycle. On-Chip Address and Control Registers. VDD= 3.3V+0.3V/-0.165V Power Supply. VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. 5V Tolerant Inputs Except I/O Pins. Byte Writable Func.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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PRELIMINARY K7A203600A Document Title 64Kx36-Bit Synchronous Pipelined Burst SRAM 64Kx36 Synchronous SRAM Revision History Rev. No. 0.0 0.1 History Initial draft Change t OH Min value from 1.3 to 1.0 at tCYC 5.0 Change t HZC Min value from 1.3 to 1.0 at tCYC 5.0 Add tCYC 183MHz, 225MHz Change DC Characteristics. Icc value from 260mA to 280mA at -72 ISB1 value from 10mA to 20mA ISB2 value from 10mA to 20mA Final spec release. Add VDDQ Supply voltage( 2.5V ) Draft Date May. 19. 1998 July. 13. 1998 Remark Preliminary Preliminary 0.2 Aug. 31. 1998 Preliminary 1.0 2.0 Nov. 16. 1998 Dec. 02. 1998 Final Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications.
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