Core
* Max fCPU: 16 MHz
* Advanced STM8A core with Harvard architecture and 3-stage pipeline
* Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block diagram . . . . . . . . . . . . . . . .

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