Core
* Max fCPU: 16 MHz
* Advanced STM8A core with Harvard architecture and 3-stage pipeline
* Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz f.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Block diagram . . . . . . . . . . . . . .

STM8AF6146

STM8AF6126

STM8AF6166

STM8AF6168

STM8AF6169

STM8AF6176

STM8AF6178

STM8AF6179

STM8AF6186

STM8AF6188

STM8AF6189

STM8AF618A

STM8AF6198

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