HYS72T64000HP3.7-B Datasheet, Qimonda AG

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* Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC ena.

capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 byt.

HYS72T64000HP3-B

HYS72T64000HP3S-B

HYS72T64000HP2.5-B

HYS72T64000HP25F-B

HYS72T64000HFA-3.7-A

HYS72T64000HFA-3S-A

HYS72T64000HFN-3.7-A

HYS72T64000HFN-3S-A

HYS72T64000HR

HYS72T64000HR-37-A

HYS72T64000HR-5-A

HYS72T64000HU

HYS72T64000HU-37-A