HYS72T512341HHP-5-B Datasheet, Qimonda

*
*
*
*
*
*
*
*
* Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling .

capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-ball I2C protocol. The first 128 by.

HYS72T512341HHP-3.7-B

HYS72T512341HJP-3.7-B

HYS72T512341HJP-5-B

HYS72T512341HKP-3.7-B

HYS72T512341HKP-5-B

HYS72T512020HR-3.7-A

HYS72T512020HR-5-A

HYS72T512022EP-3.7-B

HYS72T512022EP-3S-B

HYS72T512022HFN-3.7-A

HYS72T512022HR-3.7-A

HYS72T512022HR-3S-A

HYS72T512022HR-5-A