74HC652
Key Features
- Multiplexed real-time and stored data
- Independent register for A and B buses
- Independent enables for A and B buses
- 3-state
- Output capability: Bus driver
- Low power consumption by CMOS technology
- ICC category: MSI. APPLICATIONS
- Bus interfaces. DESCRIPTION The 74HC/HCT652 are high-speed SI-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with Jedec standard no. 7A. The 74HC/HCT652 consist of 8 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and central circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the “A” or “B” or both buses, will be stored in the internal registers, at the appropriate clock pins (CPAB or CPBA) regardless of the select pins (SAB and SBA) or output enable (OEAB and OEBA) control pins. Depending on the select inputs SAB and SBA data can directly go from input to output (real time mode) or data can be controlled by the clock (storage mode), this is when the output enable pins this operating mode permits. The output enable pins OEAB and OEBA determine the operation mode of the transceiver. When OEAB is LOW, no data transmission from An to Bn is
