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PhaseLink Corporation

PLL520-80 Datasheet Preview

PLL520-80 Datasheet

Low Phase Noise VCXO

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FEATURES
19MHz to 65MHz fundamental crystal input.
Output range: 9.5MHz – 65MHz
Complementary outputs: PECL or LVDS output.
Selectable OE Logic (enable high or enable low).
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Integrated variable capacitors.
Supports 2.5V or 3.3V Power Supply.
Available in die form.
DESCRIPTION
The PLL520-80 is a VCXO IC specifically designed to
work with fundamental crystals between 19MHz and
65MHz. The selectable divide by two feature extends
the operation range from 9.5MHz to 65MHz. It
requires very low current into the crystal resulting in
better overall stability. The OE logic feature allows
selection of enable high or enable low. Furthermore,
it provides selectable CMOS, PECL or LVDS outputs.
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
VCON Oscillator
Amplifier
XIN
w/
integrated
varicaps
XOUT
OE
Q
Q
S2
PLL520-80
PLL520-80
Low Phase Noise VCXO (9.5-65MHz)
DIE CONFIGURATION
65 mil
25 24 23 22 21 20 19 18
XIN 26
XOUT 27
Die ID:
A2020-20C
N/C 28
S2^ 29
OE
CTRL
30
VCON 31
C502A
12345 6 78
(1550,1475)
17 GNDBUF
16 CMOS
15 LVDSB
14 PECLB
13 VDDBUF
12 VDDBUF
11 PECL
10 LVDS
9 OE_SEL^
Y (0,0)
X
OUTPUT SELECTION AND ENABLE
OUT_SEL1* OUT_SEL0*
(Pad 18)
(Pad 25)
Selected Output*
0 0 High Drive CMOS
0 1 Standard CMOS
1 0 LVDS
1 1 PECL (default)
OE_SELECT OE_CTRL
(Pad 9)
(Pad 30)
State
0
0 Tri-state
1 (Default) Output enabled
1 (Default)
0 (Default) Output enabled
1 Tri-state
Pads #9, #18 & #25: Bond to GND to set to “0”,
No connection results to “default” setting
through internal pull-up.
OE_CTRL: Logical states defined by PECL levels if OE_SELECT is “1”
Logical states defined by CMOS levels if OE_SELECT is “0”
OUTPUT FREQUENCY SELECTOR
S2
0
1(Default)*
Output
Input/2
Input
*Internally set to ‘Default’ through 60Kpull-up resistor
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 011/09/04 Page 1




PhaseLink Corporation

PLL520-80 Datasheet Preview

PLL520-80 Datasheet

Low Phase Noise VCXO

No Preview Available !

www.DataSheet4U.com
PLL520-80
Low Phase Noise VCXO (9.5-65MHz)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
VDD 4.6 V
VI
-0.5 VDD+0.5
V
VO
-0.5 VDD+0.5
V
TS -65 150 °C
TA -40 85 °C
TJ 125 °C
260 °C
2 kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN. TYP. MAX. UNITS
Crystal Resonator Frequency
Crystal Loading Rating
Interelectrode Capacitance
Recommended ESR
FXIN
CL (xtal)
C0
RE
Fundamental
Die
AT cut
19 65 MHz
8* pF
5 pF
30
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific
limits.
3. Voltage Control Crystal Oscillator
PARAMETERS
SYMBOL
CONDITIONS
MIN. TYP. MAX. UNITS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
On-chip Varicaps control range
Linearity
VCXO Tuning Characteristic
VCON input impedance
VCON modulation BW
TVCXOSTB
From power valid
FXIN = 100 – 200MHz;
XTAL C0/C1 < 250
0V VCON 3.3V
VCON=1.65V, ±1.65V
VCON = 0 to 3.3V
0V VCON 3.3V, -3dB
10 ms
200* ppm
±100*
ppm
4 – 18*
pF
10* %
65 ppm/V
60 k
25 kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific
limits.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 011/09/04 Page
2


Part Number PLL520-80
Description Low Phase Noise VCXO
Maker PhaseLink Corporation
Total Page 7 Pages
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