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PhaseLink Corporation

PLL520-08 Datasheet Preview

PLL520-08 Datasheet

(PLL520-0x) Low Phase Noise VCXO

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PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
www.DataSheet4U.com
FEATURES
100MHz to 200MHz Fundamental Mode Crystal.
Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier), 400 – 800MHz (4x
multiplier), or 800MHz – 1GHz (PLL520-09
TSSOP only, 8x multiplier).
High yield design supports up to 2pF stray
capacitance at 200MHz.
CMOS (Standard drive PLL520-07 or Selectable
Drive PLL520-06), PECL (Enable low PLL520-08
or Enable high PLL520-05) or LVDS output
(PLL520-09).
Integrated variable capacitors.
Supports 3.3V-Power Supply.
Available in 16-Pin (TSSOP or 3x3mm QFN)
Note: PLL520-06 only available in 3x3mm.
Note: PLL520-07 only available in TSSOP.
PIN CONFIGURATION
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
VCON
GND
1
2
3
4
5
6
7
8
16 SEL0^
15 SEL1^
14 GND
13 CLKC
12 VDD
11 CLKT
10 GND
9 GND
DESCRIPTION
The PLL520-05/-06/-07/-08/-09 is a family of VCXO
ICs specifically designed to pull high frequency
fundamental crystals. Their design was optimized to
tolerate higher limits of interelectrode capacitance
and bonding capacitance to improve yield. They
achieve very low current into the crystal resulting in
better overall stability. Their internal varicaps allow
an on chip frequency pulling, controlled by the
VCON input.
XIN
XOUT
SEL2^
OE
12 11 10 9
13 8
14 7
P520-0x
15 6
16 5
1234
GND
CLKC
VDD
CLKT
BLOCK DIAGRAM
SEL
VCON Oscillator
Amplifier
XIN
w/
integrated
varicaps
XOUT
PLL
(Phase
Locked
Loop)
PLL by-pass
^: Internal pull-up
*: PLL520-06 pin 12 is output drive select (DRIVSEL)
(0 for High Drive CMOS, 1 for Standard Drive CMOS)
OUTPUT ENABLE LOGICAL LEVELS
OE
Part #
OE
State
Q
Q
PLL520-08
PLL520-05
0 (Default)
1
0
Output enabled
Tri-state
Tri-state
PLL520-06
PLL520-07 1 (Default) Output enabled
PLL520-09
OE input: Logical states defined by PECL levels for PLL520-08
Logical states defined by CMOS levels for PLL520-05/-06/-
07/-09
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1




PhaseLink Corporation

PLL520-08 Datasheet Preview

PLL520-08 Datasheet

(PLL520-0x) Low Phase Noise VCXO

No Preview Available !

PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
www.DataSheet4U.com
PIN DESCRIPTIONS
Name
TSSOP*
Pin number
3x3mm QFN*
Pin number
Type
Description
XIN
XOUT
OE
2
3
6
13 I Crystal in connector.
14 I Crystal out connector.
16 I Output enable pin.
VCON
7
1 I Frequency control input (0.3V to 3.0V)
GND 8,9, 10, 14
DRIVSEL**
-
CLKT
CLKC
SEL0
11
13
16
2,3,4,8,12
12
5
7
10
P Ground (except pin 12 on PLL520-06: DRIVSEL see below).
PLL520-06 only: Drive Select Input. This pin has an internal
pull-up that will default DRIVSEL to ‘1’ when not connect to
I GND. CMOS output of PLL520-06 will be high drive CMOS
when DRIVSEL is set to ‘0’, and will be standard CMOS
otherwise.
O
True output PECL (PLL520-08) or LVDS (PLL520-09)
(N/C for PLL520-07)
Complementary output PECL (PLL520-08) or LVDS
O (PLL520-09)
(CMOS out for PLL520-07).
I
SEL1
SEL2
15
5
9 I Multiplier selector pins. These pins have an internal pull-up
15 I that will default SEL to ‘1’ when not connected to GND.
SEL3
4
Not available
I
VDD 1, 12
6,11 P +3.3V power supply.
* Note: PLL520-06 only available in 3x3mm QFN, PLL520-07 only available in TSSOP.
** Note: DRIVSEL on pin 12 on PLL520-06 only.
FREQUENCY SELECTION TABLE
SEL3*
0*
1*
1*
1*
SEL2
0
0
1
1
SEL1
1
1
1
1
Note *: SEL3 is not available (always “1”) in 3x3mm package
All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.
SEL0
1
1
0
1
Selected Multiplier
Fin x 8 (PLL520-09 in TSSOP only)
Fin x 4
Fin x 2
No multiplication
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2


Part Number PLL520-08
Description (PLL520-0x) Low Phase Noise VCXO
Maker PhaseLink Corporation
Total Page 8 Pages
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