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PLL520-08 - (PLL520-0x) Low Phase Noise VCXO

Download the PLL520-08 datasheet PDF. This datasheet also covers the PLL520-05 variant, as both devices belong to the same (pll520-0x) low phase noise vcxo family and are provided as variant models within a single manufacturer datasheet.

General Description

11 SEL1^ 9 8 7 6 5 GND CLKC VDD CLKT P520-0x 2 3 4 PLL520-05/-06/-07/-08/-09 www.DataSheet4U.com Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) PIN DESCRIPTIONS Name XIN XOUT OE VCON GND DRIVSEL TSSOP Pin number 2 3 6 7 8,9, 10, 14 - 3x3mm QFN Pin numb

Key Features

  • 100MHz to 200MHz Fundamental Mode Crystal. Output range: 100.
  • 200MHz (no multiplication), 200.
  • 400MHz (2x multiplier), 400.
  • 800MHz (4x multiplier), or 800MHz.
  • 1GHz (PLL520-09 TSSOP only, 8x multiplier). High yield design supports up to 2pF stray capacitance at 200MHz. CMOS (Standard drive PLL520-07 or Selectable Drive PLL520-06), PECL (Enable low PLL520-08 or Enable high PLL520-05) or LVDS output (PLL520-09). Integrated variable capacitors.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (PLL520-05_PhaseLinkCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number PLL520-08
Manufacturer PhaseLink Corporation
File Size 275.03 KB
Description (PLL520-0x) Low Phase Noise VCXO
Datasheet download datasheet PLL520-08 Datasheet

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Other Datasheets by PhaseLink Corporation

Part Number Description
PLL520-00 Low Phase Noise VCXO
PLL520-05 (PLL520-0x) Low Phase Noise VCXO
PLL520-06 (PLL520-0x) Low Phase Noise VCXO
PLL520-07 (PLL520-0x) Low Phase Noise VCXO
PLL520-09 (PLL520-0x) Low Phase Noise VCXO

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
PLL520-05/-06/-07/-08/-09 www.DataSheet4U.com Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) PIN CONFIGURATION (Top View) VDD XIN XOUT SEL3^ SEL2^ OE VCON GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL0^ SEL1^ GND CLKC VDD CLKT GND GND FEATURES • • 100MHz to 200MHz Fundamental Mode Crystal. Output range: 100 – 200MHz (no multiplication), 200 – 400MHz (2x multiplier), 400 – 800MHz (4x multiplier), or 800MHz – 1GHz (PLL520-09 TSSOP only, 8x multiplier). High yield design supports up to 2pF stray capacitance at 200MHz. CMOS (Standard drive PLL520-07 or Selectable Drive PLL520-06), PECL (Enable low PLL520-08 or Enable high PLL520-05) or LVDS output (PLL520-09). Integrated variable capacitors. Supports 3.3V-Power Supply.