PLL103-05 buffer equivalent, 1-to-5 clock distribution buffer.
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* 5 outputs identical to FIN. Low skew (< 250 ps between outputs). Input / Output frequency range 0
– 160 MHz 25mA.
The PLL103-05 is a 1-to-5 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 5 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels.
BLOCK DIAGRAM
CLK1 CLK.
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