PLL52C61-01HA Datasheet Pentium/SDRAM Clock Generator

Manufacturer: PhaseLink

Overview: PLL52C61-01HA/-21HA Pentium/SDRAM Clock Generator with Integrated.

PLL52C61-01HA pentium/sdram clock generator by PhaseLink - Datasheet Preview

Datasheet Details

Part number	PLL52C61-01HA
Manufacturer	PhaseLink
File Size	227.41 KB
Description	Pentium/SDRAM Clock Generator
Download	PLL52C61-01HA Download (PDF)

General Description

The PLL52C61-01HA and -21HA are high performance system clock generators designed to support INTEL 430VX PCIset’s motherboard with SDRAM Pentium based systems.

All output clocks skew and jitter performance are designed to be fully compliant with INTEL Pentium CPU timing requirements.

TIMING SPECIFICATIONS PCLK-PCLK skew PCLK-BCLK skew PCLK,BCLK slew rate PCLK Jitter <250 ps 1~5 ns (PCLK leads) > 1 V/ns (0.4 ~2.4V) ±200 ps cycle-cycle BLOCK DIAGRAM PIN INFORMATION FREQUENCY SELECTION (MHz) F2 F1 F0 PCLK (0:11) BCLK(0:5) PCI=1 PCI=0 0 0 0 50 25 32 0 0 1 60 30 32 0 1 0 66.6 33.3 32 0 1 1 Test Test Test 100 55 27.5 32 101 75 37.5 32 1 1 0 83.3 41.7 32 1 1 1 68.4 34.2 32 Note: F2,F1,F0 and PCI are selectable only during Power-on.

Key Features

n Generates all clock frequencies for Pentium, AMD and Cyrix system requiring multiple CPU clocks (SDRAM, Shared memory architecture). n Supports up to12 Synchronous CPU clocks. n 6 PCI BUS clocks selectable between synchronous and asynchronous mode. n One 14.318Mhz reference clock n One 24Mhz floppy clock and one 48Mhz USB clock. n Proven power-on strapping techniques to minimize four input pins. In any cases, no glitches will be produced from the output pins during power on. n 3.3V and 5V oper.

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