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Pericom Semiconductor

PI74SSTV16857 Datasheet Preview

PI74SSTV16857 Datasheet

Registered Buffer

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PI74SSTV168571122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
14-Bit Registered Buffer
Product Features
• PI74 SSTV16857 is designed for low-voltage operation,
VDD = VDDQ = 2.3V to 2.7V
• Supports SSTL_2 Class I and II specifications
• SSTL_2 Input and Output Levels
• Designed for DDR Memory
• Flow-Through Architecture
• Package available:
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 173 mil wide plastic TVSOP (K)
Logic Block Diagram
CLK
CLK
RESET
38
39
34
D1
V REF
48
35
R
CLK
D
1 Q1
Product Description
Pericom Semiconductor’s PI74SSTV16857 series of logic circuits
are produced using the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The 14-bit PI74SSTV16857 universal bus driver is designed
for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels except for
the RESET input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock , CLK,
CLK and RESET. Data is triggered on the positive edge of CLK.
CLK must be used to maintain noise margins.
RESET must be supported with LVCMOS levels as VREF may not
be stable during power-up. RESET is asynchronous and is intended
for power-up only and when low assures that all of the registers reset
to the Low State, Q outputs are low, and all input receivers, data and
clock, are switched off.
Pericom’s PI74SSTV16857 is characterized for operation from
0° to 70°C.
TO 13 OTHER CHANNELS
Product Pin Description
Pin Name Description
RESET
Reset (Active Low)
CLK Clock Input
CLK Clock Input
D Data Input
Q Data Output
GND Ground
VDD Core Supply Voltage
VDDQ
Output Supply Voltage
VREF
Input Reference Voltage
Truth Table(1)
Inputs
Outputs
RESET CLK CLK
D
Q
L X XX L
H ↑ ↓H H
Η ↑ ↓L L
H L or H L or H X
Qo(2)
Notes:
1. H = High Signal Level
2. Output level before the
L = Low Signal Level
indicated steady state
= Transition LOW-to-HIGH input conditions were
= Transition HIGH-to-LOW established.
X = Irrelevant
Product Pin Configuration
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 48-Pin 40
10 A,K 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK
CLK
VDD
GND
VREF
RESET
D8
D9
D10
D11
D12
VDD
GND
D13
D14
1 PS8460C 06/04/01




Pericom Semiconductor

PI74SSTV16857 Datasheet Preview

PI74SSTV16857 Datasheet

Registered Buffer

No Preview Available !

PI74SSTV16857
14-Bit Registered Buffer1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Item
Storage temperature
Supply voltage
Input voltage(1)
Output voltage(1,2)
Input clamp current
Output clamp current
Continuous output current
VDD, VDDQ or GND current/pin
Package Thermal Impedance(3)
Symbol/Conditions
Tstg
VDD or VDDQ
VI
VO
IIK, VI<0
IOK, VO<0
IO, VO = 0 to VDDQ
IDD, IDDQ or IGND
θJA
Ratings
–65 to 150
–0.5 to 3.6
–0.5 to VDD +0.5
–0.5 to VDDQ +0.5
–50
±50
±50
±100
70
Units
°C
V
mA
°C/W
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Notes:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level VO > VDDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions
Parameters
Description
Min.
Nom.
Max.
Units
VDD
VDDQ
VREF
VTT
VIH
VIL
VIH
VIL
VIN
VID
VIX
IOH
IOL
TA
Supply Voltage
I/O Supply Voltage
Reference Voltage VREF = 0.5X VDDQ
Termination Voltage
DC Input High Voltage
Data Inputs
DC Input Low Voltage
Input High Voltage
Input Low Voltage
RESET
Input Voltage Level
Input Differential Voltage
CLK,CLK
Cross Point Voltage of Differential Clock Pair
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
2.3
2.3
1.15
VREF –0.04
VREF +0.15
–0.3
1.7
–0.3
–0.3
0.36
(VDDQ/2) –0.2
–20
20
0
2.5
2.5
1.25
VREF
2.7
2.7
1.35
VREF +0.04
VDDQ +0.3
VREF –0.15
VDDQ +0.3
0.8
V
VDDQ +0.6
(VDDQ/2) +0.2
mA
70 ºC
PS8460C 06/04/01
2


Part Number PI74SSTV16857
Description Registered Buffer
Maker Pericom Semiconductor
Total Page 6 Pages
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