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Pericom Semiconductor

PI74SSTVF16859 Datasheet Preview

PI74SSTVF16859 Datasheet

13-Bit to 26-Bit Registered Buffer

No Preview Available !

PI74SSTVF16859
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
13-Bit to 26-Bit Registered Buffer
Product Features
Product Description
• PI74 SSTVF16859 is designed for low-voltage operation,
2.5V for PC1600 ~ PC2700; 2.6V for PC3200
• Supports SSTL_2 Class I specifications on outputs
• All Inputs are SSTL_2 Compatible, except RESET
which is LVCMOS.
• Designed for DDR Memory
• Flow-Through Architecture
• Packages:
64-pin, 240-mil wide plastic TSSOP (A)
56-pin, Plastic Very Thin Fine Pitch Quad Flat
No Lead QFN (ZB)
Logic Block Diagram - TSSOP
48
CLK
49
CLK
RESET 51
35
D1
45
VREF
R
CLK
D
www.DataSheet4U.com
TO 12 OTHER CHANNELS
Logic Block Diagram - QFN
35
CLK
36
CLK
RESET 38
24
D1
32
VREF
R
CLK
D
16 Q1A
32 Q1B
7 Q1A
22 Q1B
Pericom Semiconductor’s PI74SSTVF16859 logic circuit is produced
using the Company’s advanced sub-micron CMOS technology,
achieving industry leading speed.
All inputs are compatible with the JEDEC standard for SSTL_2,
except the LVCMOS reset (RESET) input. All outputs are SSTL_2,
Class II compatible.
The device operates from a differential clock (CLK and CLK). Data
registered at the crossing of CLK going HIGH, and CLK going LOW.
The PI74SSTVF16859 supports low-power standby operation. When
RESET is LOW, the differential input receivers are disabled, and
undriven (floating) data, clock and reference voltage (VREF) inputs
are allowed. In addition, when RESET is LOW, all registers are reset,
and all outputs are forced LOW. The LVCMOS RESET input must
always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock
has been supplied, RESET must be held in the LOW state during
power up.
In the DDR DIMM application, RESET is specified to be completely
asynchronous with respect to CLK and CLK. Therefore, no timing
relationship can be guaranteed between the two. When entering
RESET, the register will be cleared and the outputs will be driven
LOW quickly, relative to the time to disable the differential input
receivers, thus ensuring no glitches on the output. However, when
comingoutof RESET,theregisterwillbecomeactivequickly,relative
to the time to enable the differential input receivers. When the data
inputs are LOW, and the clock is stable, during the time from the
LOW-to-HIGH transition of RESET until the input receivers
are fully enabled, the design must ensure that the outputs will
remain LOW.
Pericom’s PI74SSTVF16859 is characterized for operation from
0°C to 70°C.
TO 12 OTHER CHANNELS
Product Pin Description
Pin Name
Description
RESET
Reset (Active Low) LVCMOS
CLK Clock Input, Positive Differential Input
CLK Clock Input, Negative Differential Input
D Data Input, D1-D13
Q Data Output, Q1-Q13
GND
Ground
VDD
VDDQ
VREF
Core Supply Voltage
Output Supply Voltage
Input Reference Voltage
Truth Table(1)
Inputs
Outputs
RESET CLK
CLK
D
Q
L
X or
Floating
X or
Floating
X or
Floating
L
H ↑ ↓H
H
Η↑ ↓L
L
H L or H L or H X
Qo(2)
Notes:
1. H = High Signal Level
2. Output level before the
L = Low Signal Level
indicated steady state
= Transition LOW-to-HIGH
input conditions were
= Transition HIGH-to-LOW
established.
X = Irrelevant or floating
1
PS8657
02/13/03




Pericom Semiconductor

PI74SSTVF16859 Datasheet Preview

PI74SSTVF16859 Datasheet

13-Bit to 26-Bit Registered Buffer

No Preview Available !

PI74SSTVF16859
13-Bit to 26-Bit Registered Buffer
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Product Pin Configurations
Q13A 1
Q12A 2
64 VDDQ
63 GND
Q11A 3
62 D13
Q10A 4
61 D12
Q9A
VDDQ
GND
5
6
7
60 VDD
59 VDDQ
58 GND
Q8A 8
57 D11
Q7A 9
56 D10
Q6A 10
55 D9
Q5A 11
54 GND
Q4A 12 64-Pin 53 D8
Q3A 13
A 52 D7
Q2A 14
51 RESET
GND 15
50 GND
Q1A 16
49 CLK
Q13B 17
48 CLK
VDDQ 18
47 VDDQ
Q12B 19
46 VDD
Q11B 20
45 VREF
Q10B 21
44 D6
Q9B 22
43 GND
Q8B 23
42 D5
Q7B 24
41 D4
Q6B 25
40 D3
GND 26
39 GND
VDDQ
Q5B
Q4B
27
28
29
38 VDDQ
37 VDD
36 D2
Q3B 30
35 D1
Q2B 31
34 GND
Q1B 32
33 VDDQ
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
2 41
3 40
4 39
5 38
6
56-Pin
37
7 ZB 36
8 35
9 34
10 33
11 32
12 31
13 30
14 29
15 16 17 18 19 20 21 22 23 24 25 26 27 28
D10
D9
D8
D7
RESET
GND
CLK
CLK
VDDQ
VDD
VREF
D6
D5
D4
Maximum Ratings (Above which the useful life may be
impaired. For user guidelines, not tested.)
Item
Storage
Temperature
Symbol/
Conditions
Tstg
Ratings
–65 to 150
Units
°C
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1. The input and output negative voltage ratings may be
excluded if the input and output clamp ratings are observed.
2. This value is limited to 3.6V Maximum.
3. The package thermal impedance is calculated in accordance
with JESD 51.
Supply Voltage
Input Voltage(1,2)
Output Voltage
(1,2)
VDD or VDDQ
VI
VO
Input Clamp
Current
Output Clamp
Current
Continuous Output
Current
GVNDDD,CVuDrrDeQnt/oPrin
Package Thermal
impedance(3)
A Package
2 B-Package
oIrIKV,I V>IV<D0D
orIOVKO, V>VO <DD0Q
IOto, VVDOD=Q0
IDD I,GINDDDQ or
Ø JA
–0.5 to 3.6
–0.5 to VDD +0.5
–0.5 to VDDQ +0.5
±50
±50
±50
±100
55
24
V
mA
°C/W
2
PS8657
02/13/03


Part Number PI74SSTVF16859
Description 13-Bit to 26-Bit Registered Buffer
Maker Pericom Semiconductor
Total Page 8 Pages
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