* Member of the OmniClock Family of Programmable Clock Generators
* Operating Power Supply: 1.8 V ± 0.1 V
* I/O Standards
* Inputs: LVCMOS, Fundamental Mo.

demanding low electromagnetic interference (EMI). Using the PLL bypass mode, it is possible to get a copy of the input c.

CLK0 CLK1 CLK2 XIN/CLKIN 1 XOUT 2 PD# 3 GND 4 NB3V60113G 8 CLK2 7 VDD 6 CLK1 5 CLK0 Figure 2. Pin Connections (Top View)
  – WDFN8 www.onsemi.com 2 NB3V60113G Table 1. PIN DESCRIPTION Pin No. Pin Name Pin Type 1 XIN/CLKIN I.

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