| Description | These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad (175) versions feature complementary outputs from each flip-flop Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse Clock triggering occurs at a particular voltage lev... |
| Features |
Y LS174 contains six flip-flops with single-rail outputs Y LS175 contains four flip-flops with double-rail outputs Y Buffered clock and direct clear inputs Y Individual data input to each flip-flop Y Applications include
Buffer storage registers Shift registers Pattern generators Y Typical clock frequency 40 MHz Y Typical power dissipation per flip...
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| Datasheet |
 DM54LS175 Datasheet - 174.66KB |
