74VHC125 Datasheet | NXP Semiconductors

description The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin patible with Low-power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard JESD7-A. The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (n Y) are controlled by the output enable input (n OE). A HIGH at n OE causes the outputs to assume a high-impedance OFF-state. The 74VHC125; 74VHCT125 are identical to the 74VHC126; 74VHCT126 but have active LOW enable inputs. 2. Features I Balanced propagation delays I All inputs have a Schmitt-trigger action I Inputs accepts voltages higher than VCC I Input levels: N The 74VHC125 operates with CMOS logic levels N The 74VHCT125 operates with TTL logic levels I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Specified from - 40 °C to +85 °C and from - 40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74VHC125D 74VHCT125D - 40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm 74VHC125PW - 40 °C to +125 °C 74VHCT125PW TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74VHC125BQ - 40 °C to +125 °C 74VHCT125BQ DHVQFN14 plastic dual in-line patible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm Version SOT108-1 SOT402-1 SOT762-1 NXP Semiconductors 4. Functional diagram 74VHC125; 74VHCT125 Quad buffer/line driver; 3-state 2 1A 1Y 3 1 1OE 5 2A 2Y 6 4 2OE 9 3A 3Y 8 10 3OE 12 4A 4Y 11 13 4OE mna228 Fig 1. Logic symbol 21 1 EN1...