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SN54LS165 - 8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER

Description

The SN54/74LS165 contains eight clocked master/slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry.

Parallel data enters when the PL signal is LOW.

Features

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER The SN54 / 74LS165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputing occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new data enters via the Serial Data (DS) input. The 2-input OR clock can be used to combine two independent clock sources, or one input can act as an active LOW clock enable. SN54/74LS165 8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 CP2 15 P3 14 P2 13 P1 12 P0 11 DS 10 Q7 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.