SY100ELT23 datasheet, translator equivalent, Microchip

Features and benefits

* 3.0 ns Typical Propagation Delay
* <300 ps Typical Within-Device Skew
* Differential PECL Inputs
* 24 mA TTL Outputs
* Flow-Through Pinouts
* In.

Application

that require the translation of a clock or data signal. The ELT23 is compatible with positive ECL 100K logic levels. Pa.

Description

The SY100ELT23 is a dual differential PECL-to-TTL translator. Because PECL (positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and low skew, dual gate design make the ELT23 ideal for applications th.

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